Field of the Invention
The present invention relates to an integrated semiconductor chip.
If the area (layout structure) of an integrated semiconductor chip is considered, it is generally possible to identify so-called active regions and inactive regions on account of the structural differences in the topmost layer. By way of example, components or functional groups (for example transistors, memory cells) which effect a functionality of the semiconductor chip are disposed in the active regions; by contrast, no components or functional groups are contained in the inactive regions. With regard to the topographic construction of integrated semiconductor chips, modern fabrication processes require, in particular, homogeneous areal occupancy in all of the relevant process planes from the substrate up to and including a first metallization plane Therefore, the structural configuration of the process planes should largely be similar in the active and inactive regions of the chip. For this purpose, so-called modular dummy structures are provided within the inactive regions in the above mentioned process planes, the dummy structures being constructed similarly to the structures of the active regions. The use of modular dummy structures is already a common practice. They are primarily used for the following three reasons, reiterated briefly using key words:
a) for the production of identical layer hardnesses over the entire chip area by use of homogeneous areal occupancy underneath the respective topmost layer, important with regard to chemical mechanical polishing (CMP) and "Dishing"; PA0 b) for homogenization of exposure illumination and defraction effects over the entire chip area, optical proximity effect (OPE); and PA0 c) for homogenization and improvement of the etching process over the entire chip area, reactive ion etch (RIE) and "Micro Loading". PA0 an oxide, the substrate having trenches formed therein and the oxide disposed in and filling the trenches resulting in oxide-filled trenches; PA0 zones formed of polysilicon disposed on the substrate over an area of the oxide-filled trenches, the zones formed of polysilicon covering only part of the area of the oxide-filled trenches, the oxide-filled trenches and the zones formed of polysilicon disposed contiguously over an entire region of the chip area over which the dummy structures extend and enclose regions not having the oxide-filled trenches and the zones formed of polysilicon, the regions disposed at regular intervals and are oriented parallel in regards to each other; PA0 doping zones disposed in the substrate in the regions surrounded by the zones formed of polysilicon and the oxide-filled trenches; PA0 the electrically conductive contact points applied to the doping zones and, via the doping zones, establish electrically conductive connections with the substrate, the electrically conductive contact points covering only a part of each of the doping zones; PA0 the metal interconnects of the metallization plane are strip shaped metal interconnects oriented in a cruciform fashion at regular intervals and, in each direction, parallel to one another, and are disposed such that the metal interconnects of the metallization plane are situated in each case at right angles to one another forming crossover areas which are situated in each case above one of the electrically conductive contact points and cover the electrically conductive contact points; and PA0 the metal interconnects of the metallization plane are electrically conductively connected to the electrically conductive contact points in a region of the crossover areas.
For the operation of the semiconductor chip, it is desirable to homogenize the substrate potential of the chip as well as possible. The effect achieved by doing this is that the substrate potential is distributed uniformly for all components applied on the substrate. This results in a better, more uniform voltage supply for all the components distributed over the chip area. The wave propagation properties of voltage pulses on the electrical conductors are more predictable and more homogeneous against a uniform potential. Therefore, the wave guiding properties of superior wiring planes are also improved by a uniform substrate potential. Attempts have previously been made to achieve homogenization of the electrical substrate potential by using epitaxial substrates and by use of additional substrate contacts in the individual circuits. The known "latch-up" effect can be diminished, moreover, by using epitaxial substrates. One disadvantage of this procedure is that the application of the epitaxial layer to the substrate necessitates an additional, costly process step in the course of the fabrication process.